Motivated by inflexible specific hardware components and the increasing costs of reworking application specific integrated circuits (ASIC's), those skilled in the art have begun combining known reconfigurable devices, such as field programmable gate arrays (FPGA's), with ASIC's to exploit the benefits of both architectures and achieve systems-on-chip having an enhanced measure of flexibility and efficiency.
One such approach in this area, such as the field programmable system chip (FPSC), integrates ASIC cores into an FPGA structure while another approach embeds an FPGA or a reconfigurable logic core (RLC) as another of the proprietary cores in a system-on-chip. Both approaches, however, fail in one aspect or another. The FPSC approach fails because the FPSC dominates the chip physically thereby requiring a relatively large silicon spatial area of the system-on-chip and high power at the expense of the ASIC and its associated cores. The RLC approach fails because only a subset of the system-on-chip signals ever reach the RLC and the ones that do may not allow for the fixing of errors or the upgrading of associated hardware, for example.
Accordingly, the system-on-chip arts desire a cost-effective solution for the foregoing problems that consume little system-on-chip area and power while providing troubleshooting and hardware-upgrading flexibility.